Links Tools Info Home About reviseOmatic Careers Contact Us >Knowledge Map< Links Twitter 
Home Knowledge Map 

GCSE, AS and A Level  AS and A Level  A Level 
systems subsystems inputs (sensing) light temperature magnetic field pressure moisture sound rotation processes individual logic gates latch time delay comparator outputs lamp buzzer solenoid LED actuator servo motor loudspeaker sevensegment display transducer drivers 
systems subsystems inputs processes outputs feedback system diagrams outputs lamp buzzer solenoid LED actuator servo motor loudspeaker sevensegment display solenoid relay transducer drivers 
systems subsystems inputs processes outputs feedback system diagrams outputs lamp buzzer solenoid LED actuator servo motor loudspeaker sevensegment display solenoid relay transducer drivers 
GCSE, AS and A Level  AS and A Level  A Level 
circuit symbols measure and calculate voltage current resistance energy power multimeters timing equipment logic probes oscilloscopes rules current voltage series parallel currentvoltage characteristics V = IR P = IV P = I2R E = Pt P = V2/R 
circuit symbols measure and calculate voltage / potential difference current resistance energy power = rate of doing work multimeters timing equipment logic probes oscilloscopes rules current voltage series parallel currentvoltage characteristics V = IR P = IV P = I2R E = Pt P = V2/R RMS VRMS = Vo / √2 IRMS = Io / √2 AC Power and RMS P = IV P = I2R V2 / R 
circuit symbols measure and calculate voltage / potential difference current resistance energy power = rate of doing work multimeters timing equipment logic probes oscilloscopes rules current voltage series parallel currentvoltage characteristics V = IR P = IV P = I2R E = Pt P = V2/R RMS VRMS = Vo / √2 IRMS = Io / √2 AC Power and RMS P = IV P = I2R V2 / R 
GCSE, AS and A Level  AS and A Level  A Level 
resistors series R = R1 + R2 parallel R = R1 R2 / (R1 + R2) E24 colour codes tolerances power ratings voltage dividers VOUT = VIN R2 / (R1 + R2) sensing circuits switches photosensitive devices ntc thermistors pressure moisture sound switches pullup or pulldown logic levels potentiometers pulse generators for timing clock pulses 
resistors defined R = V / I V = I R I = V / R series R = R1 + R2 + ... parallel RT = 1 / ( 1 / R1 + 1 / R2 + ... ) R = R1 R2 / (R1 + R2) E24 colour codes tolerances power ratings voltage dividers VOUT = VIN R2 / (R1 + R2) sensing circuits switches photosensitive devices ntc thermistors pressure moisture sound characteristic curves switches pullup or pulldown logic levels potentiometers pulse generators for timing clock pulses Kirchoff current voltage Thevenin 
resistors defined R = V / I V = I R I = V / R series R = R1 + R2 + ... parallel RT = 1 / ( 1 / R1 + 1 / R2 + ... ) R = R1 R2 / (R1 + R2) E24 colour codes tolerances power ratings voltage dividers VOUT = VIN R2 / (R1 + R2) sensing circuits switches photosensitive devices ntc thermistors pressure moisture sound characteristic curves switches pullup or pulldown logic levels potentiometers pulse generators for timing clock pulses Kirchoff current voltage Thevenin 
GCSE, AS and A Level  AS and A Level  A Level 
semiconductor diode IV characteristics protection halfwave rectifier LED calculate series resistor Zener voltage regulation semiconductor switches npn transistor IC = hFE IB up to saturation VIN < 0.7 V transistor is off VBE = VIN VCE = supply voltage VIN = 0.7 V transistor is on VBE = 0.7 V VCE = 0 V nchannel MOSFET ID = gM (VGS  3) comparator IC interface to outputs 
semiconductors ntype ptype pn junction silicon diode bipolar transistor (npn) IC = hFE IB VIN < 0.7 V transistor is off VBE = VIN VCE = supply voltage VIN = 0.7 V transistor is on VBE = 0.7 V VCE = 0 V MOSFET (nchannel) gM is the IDVGS graph gradient ID = gM ( VGS  3 ) P = ID2 RDSon LED Zener diode device characteristic graphs calculations 
semiconductors ntype ptype pn junction silicon diode bipolar transistor (npn) IC = hFE IB VIN < 0.7 V transistor is off VBE = VIN VCE = supply voltage VIN = 0.7 V transistor is on VBE = 0.7 V VCE = 0 V MOSFET (nchannel) gM is the IDVGS graph gradient ID = gM ( VGS  3 ) P = ID2 RDSon LED Zener diode device characteristic graphs calculations conduction ntype ptype electrons holes pn junction forward bias reverse bias LED series resistor photodiode nchannel MOSFET bias, channel (pinching) Zener diode circuit calculations sketching characteristic graphs calculations 
GCSE, AS and A Level  AS and A Level  A Level 
logic, combinational twostates pullup and pulldown gates, up to two inputs NOT AND OR NAND NOR truth tables Boolean expressions algebra circuit simplification NAND gate redundancy identities (A.B) = A + B (A + B) = A . B 
logic, combinational twostates pullup and pulldown sourcing sinking gates, up to three inputs NOT AND OR NAND NOR XOR XNOR truth tables Boolean expressions algebra circuit simplification NAND gate redundancy identities (A.B) = A + B (A + B) = A . B de Morgan A . 1 = A A . 0 = 0 A . A = A A . A = 0 A + 1 = 1 A + 0 = A A + A = A A + A = 1 A + A . B = A + B A . B + A = A . (B + 1) = A Karnaugh maps multiplexer 
logic, combinational twostates pullup and pulldown sourcing sinking gates, up to three inputs NOT AND OR NAND NOR XOR XNOR truth tables Boolean expressions algebra circuit simplification NAND gate redundancy identities (A.B) = A + B (A + B) = A . B de Morgan A . 1 = A A . 0 = 0 A . A = A A . A = 0 A + 1 = 1 A + 0 = A A + A = A A + A = 1 A + A . B = A + B A . B + A = A . (B + 1) = A Karnaugh maps multiplexer 
GCSE, AS and A Level  AS and A Level  A Level 
logic, sequential latches BCD counter decade counter timing diagrams number systems decimal binary binarycoded decimal (BCD) counter timing diagrams conversions D type flipflop (4013) rising edge timing diagrams data transfer latch up counter 1bit 2bit timing diagrams 7seg' display (common cathode) single 4bit BCD counter decoder/driver 7segment display convert number to 7segment truth table counter reset at given value timing diagram sequence logic 4017 decade counter sequencer timing diagram 
logic, sequential
latches
BCD counter
decade counter
timing diagrams
number systems
hexadecimal
decimal
binary
binarycoded decimal (BCD)
counter
timing diagrams
conversions
D type flipflop (4013)
D, Ck, Q, Q, R, S
rising edge
timing diagrams
data transfer
latch
up counter
1 to 4 bit
timing diagrams
2 digit BCD counter
synchronous counter
7seg' display (common cathode)
single 4bit BCD counter
decoder/driver
7segment display
convert number to 7segment
truth table
counter reset at given value
timing diagram
sequence logic
4017 decade counter
sequencer
timing diagram
NAND latch
RS bistable flip flop
propagation delay
transition gates
frequency divider
asynchronous counter
4 bit counter logic controller
2 digit decimal counter & reset

logic, sequential
latches
BCD counter
decade counter
timing diagrams
number systems
hexadecimal
decimal
binary
binarycoded decimal (BCD)
counter
timing diagrams
conversions
D type flipflop (4013)
D, Ck, Q, Q, R, S
rising edge
timing diagrams
data transfer
latch
up counter
1 to 4 bit
timing diagrams
2 digit BCD counter
synchronous counter
7seg' display (common cathode)
single 4bit BCD counter
decoder/driver
7segment display
convert number to 7segment
truth table
counter reset at given value
timing diagram
sequence logic
4017 decade counter
sequencer
timing diagram
NAND latch
RS bistable flip flop
propagation delay
transition gates
frequency divider
asynchronous counter
4 bit counter logic controller
2 digit decimal counter & reset
shift register
PISO
SIPO
synchronous counter
sequence generators
Dtype flipflops
synchronous counters
state diagrams
stuck states
unused states
Boolean simplification

GCSE, AS and A Level  AS and A Level  A Level 
opamps gain calculations G = VOUT / VIN inverting G =  RF / R1 noninverting G = 1 + RF / R1 summing VOUT =  RF ( V1 / R1 + V2 / R2 + ... ) summing mixer circuit gainfrequency graph measure bandwidth from graph gain bandwidth compromise I/O voltagetime graphs normal clipping distortion typical amplifier signal source preamplifier mixer power amplifier loudspeaker 
opamps gain calculations G = VOUT / VIN inverting G =  RF / R1 noninverting G = 1 + RF / R1 summing VOUT =  RF ( V1 / R1 + V2 / R2 + ... ) summing mixer circuit comparator if (V+ > V) VOUT = V+S if (V+ < V) VOUT = VS voltage follower VOUT = VIN gainfrequency graph measure bandwidth from graph gain bandwidth compromise I/O voltagetime graphs normal clipping distortion typical amplifier signal source preamplifier mixer power amplifier loudspeaker bandwidth distortion slew rate slew rate = Δ VOUT / Δ t clean sine wave minimum slew rate = 2 π f Vp ideal opamp compare with a real one V+  V = 0 unless saturated virtual earth comparator bridge circuit balance input impedance noninverting = infinity comparator = infinity summing/inverting = R1 bandwidth is frequency range where VOUT >= VMAX / √2 gain bandwidth product 
opamps gain calculations G = VOUT / VIN inverting G =  RF / R1 noninverting G = 1 + RF / R1 summing VOUT =  RF ( V1 / R1 + V2 / R2 + ... ) summing mixer circuit comparator if (V+ > V) VOUT = V+S if (V+ < V) VOUT = VS voltage follower VOUT = VIN gainfrequency graph measure bandwidth from graph gain bandwidth compromise I/O voltagetime graphs normal clipping distortion typical amplifier signal source preamplifier mixer power amplifier loudspeaker bandwidth distortion slew rate slew rate = Δ VOUT / Δ t clean sine wave minimum slew rate = 2 π f Vp ideal opamp compare with a real one V+  V = 0 unless saturated virtual earth comparator bridge circuit balance input impedance noninverting = infinity comparator = infinity summing/inverting = R1 bandwidth is frequency range where VOUT >= VMAX / √2 gain bandwidth product 
GCSE, AS and A Level  AS and A Level  A Level 
capacitors farad coulomb 
capacitors farad coulomb capacitance definition from C = Q / V Q = C V V = Q / C series CT = 1 / ( 1 / C1 + 1 / C2 + ... ) CT = C1 C2 / (C1 + C2 ) parallel CT = C1 + C2 + ... 
capacitors farad coulomb capacitance definition from C = Q / V Q = C V V = Q / C series CT = 1 / ( 1 / C1 + 1 / C2 + ... ) CT = C1 C2 / (C1 + C2 ) parallel CT = C1 + C2 + ... 
GCSE, AS and A Level  AS and A Level  A Level 
timing period frequency f = 1 / T RC Circuit capacitors charging discharging voltage time graph 555 timer monostable T = 1.1 R C astable f = 1.44 / ( ( R1 + 2R2 ) C ) markspace ratio TON / TOFF = ( R1 + R2 ) / R2 measure amplitude period 
timing period frequency f = 1 / T RC Circuit capacitors charging discharging voltage time graph 555 timer monostable T = 1.1 R C astable tH = 0.7 ( R1 + R2 ) C tL = 0.7 R2 C f = 1.44 / ( ( R1 + 2R2 ) C ) markspace ratio TON / TOFF = ( R1 + R2 ) / R2 measure amplitude period RC time constant = RC graphs logarithmic axes T50% = 0.69 R C T63% = R C = (T37% discharging) T66% = 1.1 R C (555 mono) T100% = 5 R C charging VC = V0 ( 1  e(1 / RC) ) t =  R C ln( 1  VC / V0 ) discharging VC = V0 e( R C) t =  R C ln( VC / V0 ) RC debouncing Schmitt trigger astable F ≈ 1 / (R C ) 
timing period frequency f = 1 / T RC Circuit capacitors charging discharging voltage time graph 555 timer monostable T = 1.1 R C astable tH = 0.7 ( R1 + R2 ) C tL = 0.7 R2 C f = 1.44 / ( ( R1 + 2R2 ) C ) markspace ratio TON / TOFF = ( R1 + R2 ) / R2 measure amplitude period RC time constant = RC graphs logarithmic axes T50% = 0.69 R C T63% = R C = (T37% discharging) T66% = 1.1 R C (555 mono) T100% = 5 R C charging VC = V0 ( 1  e(1 / RC) ) t =  R C ln( 1  VC / V0 ) discharging VC = V0 e( R C) t =  R C ln( VC / V0 ) RC debouncing Schmitt trigger astable F ≈ 1 / (R C ) 
GCSE, AS and A Level  AS and A Level  A Level 
interfacing analogue digital conversion using transistor (npn) MOSFET comparator Schmitt inverter debouncing analogue hysteresis 
interfacing analogue digital conversion using transistor (npn) MOSFET comparator Schmitt inverter debouncing analogue hysteresis signal conditioning voltage dividers photosensitive devices ntc thermistors switches 
interfacing analogue digital conversion using transistor (npn) MOSFET comparator Schmitt inverter debouncing analogue hysteresis signal conditioning voltage dividers photosensitive devices ntc thermistors switches 
GCSE, AS and A Level  AS and A Level  A Level 
microcontroller (PIC) programmable integrated circuit interfacing inputs outputs programming flowchart applications vehicles domestic appliances advantages flowcharts start/end process input/output decision/yes/no loop 
microcontroller (PIC) programmable integrated circuit interfacing inputs outputs programming flowchart applications vehicles domestic appliances advantages flowcharts start/end process input/output decision/yes/no loop 
microcontroller (PIC) programmable integrated circuit interfacing inputs outputs programming flowchart assembler language applications vehicles domestic appliances advantages flowcharts start/end process input/output decision/yes/no loop structure programmable memory input ports output ports CPU clock reset interrupts and polling external device request service on request 
GCSE, AS and A Level  AS and A Level  A Level 
power supplies rectification half wave full wave regulation line ? load ? Zener diode alone with emitter follower ? with noninverting amplifier ? smoothing capacitors ripple voltage Vr = 1 / ( fr C ) VOUT load graph 
power supplies rectification half wave full wave regulation line load Zener diode alone with emitter follower with noninverting amplifier smoothing capacitors ripple voltage Vr = 1 / ( fr C ) VOUT load graph noninverting amplifier gain equation VL ≈ VZ ( 1 + RF / R1 ) 

A Level  A Level  A Level 
AC Circuits and Passive Filters RC and LC circuits resistive loads use Vt, It and Pt graphs impedance of passive filters highpass lowpass bandpass RMS and Peak series circuit impedance XC = 1 / ( 2 π f C ) XL = 2 π f L Z = √( R2 + X2 ) passive RC filters recognise analyse design draw circuits graphs linearlog loglog buffering passive LC filter (tuned circuit) resonant frequency f0  1 / ( 2 π √( L C ) ) dynamic resistance RD = L / ( rL C ) Q factor Q = f0 / bandwidth Q = 2 f0 L / rL 
signal conversion digital to analogue analogue to digital ADC compare comparator digital ramp flash ADC priority encoders comparators 2n  1 calculation DAC summing circuit specification signals communications microprocessors digitise audio  ramp video  flash sampling rate bit rate resolution = i/p voltage range / 2n 
communication systems meaningful information transmitted from A received at B structure information source transmitter/encoder transmission medium amplifier/regenerator receiver/decoder information destination wireless transmission digital communication optical communication calculate bandwidth data rate gain noise distortion bandwidth (bw) data rate informationcarrying capacity number of channels NCH = available bw / channel bw max data rate = 2 x available bw multiplexing many signals one transmission channel one transmission medium frequency division multiplexing time division multiplexing filter limit information signal bw decibel scale power gain attenuation (power loss) Gdb = 10 log10 ( POUT / PIN ) combined gain of several stages signal to noise ratio power and voltage SNRdb = 10 log10 ( PS / PN ) SNRdb = 20 log10 ( VS / VN ) attenuation in db SNR in db 
A Level  A Level  A Level 
wireless transmission radio spectrum LF, MF, HF, VHF, UHF, SHF frequency channels data transmission bandwidth requirements availability calculations amplitude modulation (AM) modulation % depth m% = 100 ( Vmax  Vmin ) / ( Vmax  Vmin ) frequency modulation (FM) modulation index β = Δf0 / f1 transmitted bandwidth (bw) bw = 2 ( Δf0 + f1 ) bw = 2 ( 1 + β ) f1 waves electromagnetic sound λ = wavelength f = frequency c = speed of the wave c = speed of light (radio) c = f λ modulation graphs, sine wave AM FM 
instrumentation instrumentation amplifiers opamps difference amplifier VOUT = VDIFF ( RF / R1 ) bridge circuits thermistors strain gauges sensing rotational speed slotted discs sensing angular position encoded discs Binary code Gray code advantage logic system process slotted disc output process encoded discs output 
digital communication types of modulation (graphs) pulse code (PCM) transmitter block diagram low pass filter sampling gate sampling clock ADC PISO shift register PISO clock receiver block diagram Schmitt trigger SIPO shift register SIPO clock DAC low pass filter pulse amplitude (PAM) pulse position (PPM) regeneration of digital signals Schmitt trigger circuit Nyquist theorem fSampling = 2 fMax Signal Frequency time division multiplexing (TDM) improved PCM link capacity bit rate (br) number of channels Nchannels br = fSampling x Nbits per sample x Nchannels 
A Level  A Level  A Level 
optical communication convert signals electrical optical LED LASER photodiode glass fibres refractive index total internal reflection singlemode multimode dispersion attenuation latency radiation losses 
high power switching DC loads AC loads thyristor DC characteristics holding current minimum gate voltage minimum gate current capacitor commutation diac RC network AC phase control circuit graphs triac RC network AC phase control circuit graphs phase shift supply and capacitor voltage Φ = tan1 ( R / XC ) advantages over transistor MOSFET relay 
audio systems amplifier preamplifier power amplifiers pushpull mixer summing amplifier opamp active filters inverting first order tone control bass boost treble boost bass cut treble cut break frequency fb  1 / ( 2 π R C ) multistage voltage preamplifier bandwidth gain summing amplifier emitter follower VOUT = VIN  0.7 source follower VOUT = VIN  3 but it depends on the MOSFET loudspeaker maximum power transfer theorem pushpull power amplifier emitter follower source follower maximum power PMAX = VS2 / ( 8 RL ) graphs and waveforms active filter frequencies emitter follower source follower pushpull cross over distortion clipping/limiting/saturation reduce distortion biasing negative feedback slew rate distortion 
Contact, Copyright, Cookies and Legalities: C Neil Bauers  reviseOmatic V4  © 2016/17
Hosted at linode.com  London