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AS Level     Sequential Logic     Synchronous Counter     >Up Counter and Reset<    

Sequential Logic Up Counter and Reset


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  AS Level    Sequential Logic  0 of 11    Question 736    Counter Controller 
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Deadline not set1 of 11    Question 541    D Type Flip Flop Counters 
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Deadline not set2 of 11    Question 542    D Type Flip Flop Counters 
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Deadline not set3 of 11    Question 543    D Type Flip Flop Counters 
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Deadline not set4 of 11    Question 545    D Type Flip Flop Counters 
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Deadline not set5 of 11    Question 546    D Type Flip Flop Counters 
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Deadline not set6 of 11    Question 673    RS Flip Flop 01 
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Deadline not set7 of 11    Question 672    RS Flip Flop 02 
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Deadline not set8 of 11    Question 671    RS Flip Flop 03 
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Deadline not set9 of 11    Question 674    RS Flip Flop 04 
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Deadline not set10 of 11    Question 675    RS Flip Flop 05 
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Deadline not set11 of 11    Question 676    RS Flip Flop 06 
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Deadline not set  Questions 0 to 11   -->  View All  

On the rising edge of the clock pulse, the input (D) is copied to the output (Q).
Since Q is connected to D, the output is inverted on the rising edge.

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external pulse.
All subsequent flip-flops are clocked by the output of the preceding flip-flop.
The counter output might be momentarily wrong until the clock pulse has reached every the flip-flop.
This takes about 20 nanoseconds per flip-flop.

A One Bit Counter using a D Type Flip Flop

In decimal this counts 0 1 0 1 0 1 and in binary, it's the same.

D Type Flip Flop One Bit Counter

View counter in the Lushprojects Simulator.

A Two Bit Counter using Two D Type Flip Flops

In decimal, this counter counts 0 1 2 3 0 1 2 3 0 1 2 3 and in binary, 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 .

D Type Flip Flop Two Bit Counter

View counter in the Lushprojects Simulator.

A Four Bit Counter with Reset - Alter it to reset on Ten

This counter goes from zero to five. On reaching six, a microsecond later it has reset to zero. Alter it to count up to nine. The reset should detect ten and cause the reset.

The AND gate is wired to detect six in decimal or in binary, 0 1 1 0. The gate output goes high and the flip flops all reset.

To reset on ten, the binary is 1 0 1 0 but beware! The flip flops are back to front in the diagram so you need 0 1 0 1 with bit values 1 2 4 8.

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