Site Logo Home
 
rOm
Quest
Glossary
 
Random
Page
Search
Site
Lush
Sim
Class
Subject
Images
 
Help
FAQ
Sign
Up
Log
In
AS Level     Logic     Algebra     Bistable Latch     Karnaugh Maps     Multiplexing     NOR Array     >Propagation Delay<    

Logic Propagation Delay


Site for Eduqas/WJEC - Go to the AQA site.

  AS Level    Combinational Logic  0 of 26    Question 921    Gate Arrays 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set1 of 26    Question 927    Gate Arrays 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set2 of 26    Question 928    Gate Arrays 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set3 of 26    Question 929    Gate Arrays 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set4 of 26    Question 930    Gate Arrays 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set5 of 26    Question 931    Gate Arrays 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set6 of 26    Question 934    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set7 of 26    Question 935    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set8 of 26    Question 936    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set9 of 26    Question 937    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set10 of 26    Question 938    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set11 of 26    Question 939    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set12 of 26    Question 940    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set13 of 26    Question 941    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set14 of 26    Question 942    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set15 of 26    Question 943    Karnaugh Maps 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set16 of 26    Question 122    Logic Gate Rules 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set17 of 26    Question 123    Logic Gate Rules 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set18 of 26    Question 124    Logic Gate Rules 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set19 of 26    Question 125    Logic Gate Rules 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set20 of 26    Question 146    Logic Gate Rules 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set21 of 26    Question 573    Truth Tables 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set22 of 26    Question 576    Truth Tables 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set23 of 26    Question 577    Truth Tables 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set24 of 26    Question 126    Truth Tables 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set25 of 26    Question 127    Truth Tables 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set26 of 26    Question 128    Truth Tables 
Score 0/0 
Not attempted  
Last Answer  
Deadline not set  Questions 0 to 26   -->  View All  

A 4000 series CMOS gate might have a propagation delay of about 10 nanoseconds.
This is the time taken for the signal to get through the gate.
This time is sometimes called latency.
It depends on the load capacitance. This load has to be charged or discharged.
Smaller load capacitances lead to faster chips.

Even wires have a propagation delay.
This is because the signals travel at the speed of light or a bit slower on circuit boards.
Computer mother-board and other high speed digital designs have to take these delays into account.

This circuit has two paths. The one with the extra NOT gates adds an extra 20 nanosecond delay. The XOR gate output will have a 20 nanosecond pulse output. Unwanted pulses like this are called GLITCHES. If you need a very short pulse, this circuit becomes useful.

With equal inputs, the XOR gate output should always be LOW. The two NOT gates cancel each other out so the XOR gate should always have equal inputs. This is almost true but the time delay leads to non-equal inputs for a few nanoseconds. This causes the glitch.

Propagation Delay Glitch

This simulation exagerates the propagation delay by adding large load capacitances. The glitch is very obvious.

Subject Name     Level     Topic Name     Question Heading     First Name Last Name Class ID     User ID    

fff
Home
<<<
ppw
Pg Up
<<
ppp
Up
<
|||

>|<
nnn
Down
>
nnw
Pg Down
>>
lll
End
>>>

Close
Escape
X

Q: qNum of last_q     Q ID: Question ID         Score: num correct/num attempts         Date Done    

 

Submit
Enter

 

Question Text

image url

 


Help Link

Add     Delete     Clone     Edit     Hardness

Help Text
Debug


 

 

 

Contact, Copyright, Cookies and Legalities: C Neil Bauers - reviseOmatic V4 - © 2016/17

Hosted at linode.com - London