AS Level    Combinational Logic    Questions 0 to 26   -->  View All  

A 4000 series CMOS gate might have a propagation delay of about 10 nanoseconds.
This is the time taken for the signal to get through the gate.
This time is sometimes called latency.
It depends on the load capacitance. This load has to be charged or discharged.
Smaller load capacitances lead to faster chips.

Even wires have a propagation delay.
This is because the signals travel at the speed of light or a bit slower on circuit boards.
Computer mother-board and other high speed digital designs have to take these delays into account.

This circuit has two paths. The one with the extra NOT gates adds an extra 20 nanosecond delay. The XOR gate output will have a 20 nanosecond pulse output. Unwanted pulses like this are called GLITCHES. If you need a very short pulse, this circuit becomes useful.

With equal inputs, the XOR gate output should always be LOW. The two NOT gates cancel each other out so the XOR gate should always have equal inputs. This is almost true but the time delay leads to non-equal inputs for a few nanoseconds. This causes the glitch.

This simulation exagerates the propagation delay by adding large load capacitances. The glitch is very obvious.