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GCSE     Logic     >Algebra<     Gates     Latch     NAND Array     Schmitt NOT     Truth Tables    

Logic Algebra


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  GCSE    Combinational Logic  0 of 56    Question 191    Boolean AND Symbol 
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Deadline not set1 of 56    Question 612    Boolean Expressions 
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Deadline not set2 of 56    Question 613    Boolean Expressions 
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Deadline not set4 of 56    Question 615    Boolean Expressions 
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Deadline not set5 of 56    Question 616    Boolean Expressions 
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Deadline not set6 of 56    Question 190    Boolean OR Symbol 
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Deadline not set7 of 56    Question 926    Gate Arrays 
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Deadline not set8 of 56    Question 922    Gate Arrays 
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Deadline not set9 of 56    Question 923    Gate Arrays 
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Deadline not set11 of 56    Question 925    Gate Arrays 
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Deadline not set12 of 56    Question 1477    Logic 
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Deadline not set13 of 56    Question 1478    Logic 
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Deadline not set14 of 56    Question 1479    Logic 
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Deadline not set15 of 56    Question 1480    Logic 
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Deadline not set16 of 56    Question 1482    Logic Algebra 
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Deadline not set17 of 56    Question 1481    Logic Algebra 
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Deadline not set18 of 56    Question 1277    Logic Gates 
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Deadline not set19 of 56    Question 1275    Logic Gates 
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Deadline not set20 of 56    Question 1278    Logic Gates 
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Deadline not set21 of 56    Question 1279    Logic Gates 
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Deadline not set22 of 56    Question 1280    Logic Gates 
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Deadline not set23 of 56    Question 1281    Logic Gates 
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Deadline not set24 of 56    Question 1282    Logic Gates 
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Deadline not set25 of 56    Question 1283    Logic Gates 
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Deadline not set26 of 56    Question 1284    Logic Gates 
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Deadline not set27 of 56    Question 1285    Logic Gates 
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Deadline not set28 of 56    Question 117    Logic Gates 
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Deadline not set29 of 56    Question 249    Logic Gates 
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Deadline not set30 of 56    Question 116    Logic Gates 
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Deadline not set31 of 56    Question 118    Logic Gates 
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Deadline not set32 of 56    Question 119    Logic Gates 
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Deadline not set33 of 56    Question 120    Logic Gates 
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Deadline not set34 of 56    Question 121    Logic Gates 
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Deadline not set35 of 56    Question 245    Logic Gates 
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Deadline not set36 of 56    Question 246    Logic Gates 
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Deadline not set37 of 56    Question 247    Logic Gates 
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Deadline not set38 of 56    Question 248    Logic Gates 
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Deadline not set39 of 56    Question 250    Logic Gates 
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Deadline not set40 of 56    Question 1491    Logic Latch 
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Deadline not set41 of 56    Question 1484    Logic Latch 
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Deadline not set42 of 56    Question 1485    Logic Latch 
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Deadline not set43 of 56    Question 1486    Logic Latch 
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Deadline not set44 of 56    Question 1487    Logic Latch 
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Deadline not set45 of 56    Question 1488    Logic Latch 
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Deadline not set46 of 56    Question 1489    Logic Latch 
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Deadline not set47 of 56    Question 1490    Logic Latch 
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Deadline not set48 of 56    Question 1483    Logic Latch 
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Deadline not set49 of 56    Question 306    Sub-systems 
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Deadline not set50 of 56    Question 1018    Subsystems 
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Deadline not set51 of 56    Question 1017    Subsystems 
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Deadline not set52 of 56    Question 1016    Subsystems 
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Deadline not set53 of 56    Question 569    Truth Tables 
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Deadline not set54 of 56    Question 570    Truth Tables 
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Deadline not set55 of 56    Question 571    Truth Tables 
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Deadline not set56 of 56    Question 572    Truth Tables 
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Techniques

If you have a good understanding of the logic gate rules, it is possible to work out a simpler solution just by examining the truth table and thinking hard. But this is a rather hit and miss approach and Karnaugh maps and Boolean algebra can be faster and more reliable methods but neither is easy.

Boolean algebra can be used to simplify expressions/circuits to generate a more optimal solution.

Everyone

De Morgan Boolean Identities

Gates These are the same

Gates These are the same

De Morgan


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