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• On the rising edge of the clock pulse, the input D is copied to the output Q.
  The data is stored until the next rising edge.
  At any time, the chip can be SET or RESET with a HIGH pulse on S or R.
   
• This is called edge triggered. If the DATA input changes between clock pulses, this has no effect on the output.
• The rising edge of the clock pulse stores the input bit so this flip flop can be used as a data latch (memory).
• A single D Type Flip Flop can store one bit.
• On the rising edge of the clock pulse,
       if D = 1 the circuit is "SET and Q goes high
       if D = 0 the circuit is "RESET" and Q goes low.
       Not Q is always in the opposite state to Q.

Here is the symbol of a D Type Flip Flop.

• The device can be set or reset at any time by setting the S or R inputs high.
• This applies to AQA exam questions and 4000 series gates.
• If you use 74xxx gates in your project, these come with Set and Reset inputs where low signals are needed.
  

Data Latch

• On the rising edge of the clock pulse, the data on D0, D1, D2 and D3 is copied to Q0, Q1, Q2 and Q3.
• Data latches are needed to store data that is only available or valid for a short time.
• For example data from the parallel port may not be valid for long.
• If this data is latched (stored), the latch output remains available for as long as necessary.
• The data remains valid until the next clock pulse.