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A Level     Microcontroller     Architecture     >Instruction Set<     Memory     ~ BSF and BCF     ~ Call and Return     ~ COMF     ~ Counting     ~ Heater     ~ INCF and BTFSC     ~ INT0IF     ~ LED Matrix     ~ Motor     ~ Stepper Motor    

Microcontroller Instruction Set


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Microchip 8 bit microcontrollers have a reduced instruction set with only 32 instructions for arithmetic, logic, data moves and simple decisions.

The Microchip Instruction Set Data Sheet contains detailed information about each available instruction.

GOTO Fail    Thanks xkcd.

The Instruction Set

Mnemonics in UPPER CASE are included in the WJEC/Eduqas data Booklet.    PIC16F88 Data Sheet See page 150.
(* NOP) SLEEP and CLRWDT run as NOP operations. The releatd registers and flags have not been implemented.

Op Operand/s Description                Cycles Bits               Flags     Included in the WJEC Data Booklet
|       |    |                            |    |                  |         |
|       |    |                            |    |                  |         |
config1 -    Config Register at 0x02      0    11 1111 0101 0000  |         |   
config2 -    Config Register at 0x03      0    11 1111 1111 1111  |         |   
                                                                  |         |
clrw    -    Clear W                      1    00 0001 0xxx xxxx  Z         |   
clrwdt  -    Clear Watchdog Timer (* NOP) 1    00 0000 0110 0100     TO,PD  |   
NOP     -    No Operation                 1    00 0000 0xx0 0000            WJEC
RETFIE  -    Return from interrupt        2    00 0000 0000 1001            WJEC
RETURN  -    Return from Subroutine       2    00 0000 0000 1000            WJEC
sleep   -    Go into Standby mode (* NOP) 1    00 0000 0110 0011     TO,PD      

CLRF    f    Clear f                      1    00 0001 lfff ffff  Z         WJEC
MOVWF   f    Move W to f                  1    00 0000 lfff ffff            WJEC

BCF     f, b Bit Clear f                  1    01 00bb bfff ffff            WJEC
BSF     f, b Bit Set f                    1    01 01bb bfff ffff            WJEC
BTFSC   f, b Bit Test f, Skip if Clear    1(2) 01 10bb bfff ffff            WJEC
BTFSS   f, b Bit Test f, Skip if Set      1(2) 01 11bb bfff ffff                

addwf   f, d Add W and f                  1    00 0111 dfff ffff  Z, DC, C      
andwf   f, d AND W with f                 1    00 0101 dfff ffff  Z             
COMF    f, d Complement f                 1    00 1001 dfff ffff  Z         WJEC
decf    f, d Decrement f                  1    00 0011 dfff ffff  Z             
DECFSZ  f, d Decrement f, Skip if 0       1(2) 00 1011 dfff ffff            WJEC
INCF    f, d Increment f                  1    00 1010 dfff ffff  Z         WJEC
incfsz  f, d Increment f, Skip if 0       1(2) 00 1111 dfff ffff                
iorwf   f, d Inclusive OR W with f        1    00 0100 dfff ffff  Z             
MOVF    f, d Move f                       1    00 1000 dfff ffff  Z             
rlf     f, d Rotate Left f through Carry  1    00 1101 dfff ffff         C      
rrf     f, d Rotate Right f through Carry 1    00 1100 dfff ffff         C      
subwf   f, d Subtract W from f            1    00 0010 dfff ffff  Z, DC, C      
swapf   f, d Swap nibbles in f            1    00 1110 dfff ffff                
xorwf   f, d Exclusive OR W with f        1    00 0110 dfff ffff  Z             

ADDLW   k    Add literal and W            1    11 111x kkkk kkkk  Z, DC, C  WJEC
ANDLW   k    AND literal with W           1    11 1001 kkkk kkkk  Z         WJEC
CALL    k    Call subroutine              2    10 0kkk kkkk kkkk            WJEC
GOTO    k    Go to address                2    10 1kkk kkkk kkkk            WJEC
IORLW   k    Inclusive OR literal with W  1    11 1000 kkkk kkkk  Z         WJEC
MOVLW   k    Move literal to W            1    11 00xx kkkk kkkk            WJEC
retlw   k    Return with literal in W     2    11 01xx kkkk kkkk                
SUBLW   k    Subtract W from literal      1    11 110x kkkk kkkk  Z, DC, C  WJEC
xorlw   k    Exclusive OR literal with W  1    11 1010 kkkk kkkk  Z             

CONSTANTS DEFINED IN THE HEADER FILE

W       EQU       0
F       EQU       1

; ===== INTCON =====
GIE     EQU    0x80    ; Global Interrupt Enable
PEIE    EQU    0x40    ;       Peripheral Interrupt Enable          (not implemented)
TMR0IE  EQU    0x20    ;       Timer 0 Interrupt Enable             (not implemented)
INT0IE  EQU    0x10    ; INT0 Interrupt Enable, used with RB0/INT
RBIE    EQU       8    ;       RB or Port B Change Interrupt Enable (not implemented)
TMR0IF  EQU       4    ;       Timer 0 Interrupt FLAG (not used)
INT0IF  EQU       2    ; INT0 Interrupt FLAG, used with RB0/INT
RBIF    EQU       1    ;       RB or Port B Interrupt FLAG          (not implemented)

; ===== STATUS =====
IRP     EQU    0x80    ;                                            (not implemented)
RP1     EQU    0x40    ;                                            (not implemented)
RP0     EQU    0x20    ;                                            (not implemented)
TO      EQU    0c10    ;                                            (not implemented)
PD      EQU       8    ;                                            (not implemented)
Z       EQU       4    ; Zero flag is set if a move or calculation gives a zero result.
DC      EQU       2    ;                                            (not implemented)
C       EQU       1    ; Carry flag is set if a calculation gives a negative result or one too big to fit in 8 bits.

; ===== SPECIAL PURPOSE REGISTER ADDRESSES =====
PCL     EQU       2    ; The Program Counter
STATUS  EQU       3    ; The Status Register
PORTA   EQU       5    ; PORTA for I/O
PORTB   EQU       6    ; PORTB for I/O
TRISA   EQU       5    ; Data Direction for PORTA
TRISB   EQU       6    ; Data Direction for PORTB
INTCON  EQU    0x0B    ; The Interrupt Controller Register

Literals can be ...

0x25 (25 hexadecimal - recommended)
h'25' (25 hexadecimal)
d'37' (37 as a normal decimal number)
37 (a normal decimal mumber)
b'00100101' (a binary number which just happens to be 37 or 0x25 - recommended)

MyCount EQU 0x22    Literals can be given a name. Here the general purose register at address 0x22 is named MyCount.

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