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A Slow But Low Cost Analogue to Digital Converter
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This type of Analogue to Digital Converter is fairly slow (but cheap and simple).
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It is ideal for data that changes fairly slowly such as vehicle or aircraft control systems.
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Audio signals are also slow enough to be converted.
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To convert video, a flash ADC is needed.
Falstad Simulation
The Circuit
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The output of a binary counter is connected to a DAC.
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This produces a ramp wave.
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A comparator is used to compare the ramp with the signal to be converted.
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When the comparator changes state, the binary data is latched.
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In this way the analogue input is converted to binary numbers.
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The diagram below shows a 4 bit ADC. 8, 12 and 16 bit converters are more common.
|
8 |
4 |
2 |
1 |
|
|
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
0 |
1 |
1 |
|
0 |
0 |
1 |
0 |
2 |
|
0 |
0 |
1 |
1 |
3 |
|
0 |
1 |
0 |
0 |
4 |
|
0 |
1 |
0 |
1 |
5 |
|
0 |
1 |
1 |
0 |
6 |
|
0 |
1 |
1 |
1 |
7 |
|
1 |
0 |
0 |
0 |
8 |
|
1 |
0 |
0 |
1 |
9 |
|
1 |
0 |
1 |
0 |
10 |
|
1 |
0 |
1 |
1 |
11 |
|
1 |
1 |
0 |
0 |
12 |
|
1 |
1 |
0 |
1 |
13 |
|
1 |
1 |
1 |
0 |
14 |
|
1 |
1 |
1 |
1 |
15 |
The ramp is this way up because the summing amplifier used in the DAC is also an inverting amplifier.
Ramp ADC Problems
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There is a time delay after the start pulse because the counter has to reach the correct value.
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When the comparator changes state, the conversion is complete.
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This could happen quickly or take longer if most of the ramp has to be compared.
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The delay depends on
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the clock speed and
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the value of the data input.
Typical ADC Chips
All the components above are built into one chip. This has pins to ...
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SC - start the conversion
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EoC - signal the end of conversion.
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During the conversion, the output is not valid.
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The EoC (end of conversion) signal indicates when the conversion is complete.
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OE - enable the output. This is tristate logic. When the output is enabled, the ADC data can be copied to the data bus.
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